1. Field of the Invention
The present invention relates to an electronic circuit, and more particularly to a circuit having a constant delay time regardless of the variation in a driving voltage.
2. Description of the Prior Art
Generally, a certain time is required when an electronic signal is transmitted, which is typically the time that the signal is delayed.
FIG. 1 is a circuit diagram of a conventional delay circuit. As shown in this drawing, the conventional delay circuit comprises an inverter 10 for inverting an input signal IN, a capacitor 11 connected to an output terminal of the inverter 10 in parallel and an inverter 12 for inverting the output signal from the inverter 10 so as to generate a delayed signal OUT.
The delay circuit of FIG. 1 is adapted to delay the input signal IN using a RC delay according to the turn-on resistance of an electric wire and a capacitance of the capacitor 11 wherein the delay time is determined mainly by the capacitance thereof.
If a voltage applied to the capacitor 11 is varied, an amount of current flowing through the output terminal of the inverter 10 and the capacitor 11 is varied, too. Accordingly, the time for charging the capacitor 11 becomes diverse resulting in a variation in the delay time. Typically, the current is proportional to a square of driving voltage and the capacitance to the driving voltage. Thus, the driving voltage should be maintained constantly to keep the delay time fixed, which is difficult in actuality. As a result, there is a need for a delay circuit which can have a constant delay time regardless of the variation in the driving voltage.